Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
Michael D. Powell,
Se-Hyun Yang,
B. Falsafi,
K. Roy,
T. N. Vijaykumar
|
9 |
2000 |
9
2000
|
RAPL: Memory power estimation and capping
Howard David,
E. Gorbatov,
U. Hanebutte,
R. Khanna,
C. Le
|
9 |
2010 |
9
2010
|
Clustered voltage scaling technique for low-power design
K. Usami,
M. Horowitz
|
8 |
1995 |
8
1995
|
Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks
Zhanping Chen,
Mark C. Johnson,
Liqiong Wei,
K. Roy
|
8 |
1998 |
8
1998
|
Cache design trade-offs for power and performance optimization: a case study
Ching-Long Su,
A. Despain
|
8 |
1995 |
8
1995
|
Analytical energy dissipation models for low-power caches
M. Kamble,
K. Ghose
|
8 |
1997 |
8
1997
|
AxNN: Energy-efficient neuromorphic systems using approximate computing
Swagath Venkataramani,
Ashish Ranjan,
K. Roy,
A. Raghunathan
|
7 |
2014 |
7
2014
|
A Robust and Energy-Efficient Classifier Using Brain-Inspired Hyperdimensional Computing
Abbas Rahimi,
P. Kanerva,
J. Rabaey
|
7 |
2016 |
7
2016
|
Minimizing data center cooling and server power costs
E. Pakbaznia,
Massoud Pedram
|
7 |
2009 |
7
2009
|
Powering the Internet of Things
Y. Ramadass
|
7 |
2014 |
7
2014
|
2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits
A. Kramer,
J. Denker,
B. Flower,
J. Moroney
|
7 |
1995 |
7
1995
|
Energy-Efficient CNN Implementation on a Deeply Pipelined FPGA Cluster
Chen Zhang,
Di Wu,
Jiayu Sun,
Guangyu Sun,
Guojie Luo,
J. Cong
|
7 |
2016 |
7
2016
|
Analyzing static and dynamic write margin for nanometer SRAMs
Jiajing Wang,
Satyanand Nalam,
B. Calhoun
|
7 |
2008 |
7
2008
|
Guarded evaluation: pushing power management to logic synthesis/design
V. Tiwari,
S. Malik,
P. Ashar
|
7 |
1995 |
7
1995
|
